Memory devices are typically provided as internal storage areas in the computer. There are several different types of memory. One type of memory is random access memory (RAM) that is typically used as main memory in a computer environment. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents.
A dynamic random access memory (DRAM) is made up of memory cells. Each cell of a modern DRAM includes a transistor and a capacitor, where the capacitor holds the value of each cell, namely a “1” or a “0,” as a charge on the capacitor. Because the charge on a capacitor gradually leaks away, DRAM capacitors must be refreshed on a regular basis. A memory device incorporating a DRAM memory includes logic to refresh (recharge) the capacitors of the cells periodically or the information will be lost. Reading the stored data in a cell and then writing the data back into the cell at a predefined voltage level refreshes a cell. The required refreshing operation is what makes DRAM memory dynamic rather than static.
The transistor of a DRAM cell is a switch to let control circuitry for the RAM either read the capacitor value or to change its state. The transistor is controlled by a row line coupled to its gate connection. In a read operation, the transistor is activated and sense amplifiers coupled to bit lines (column) determine the level of charge stored in the memory cell capacitor, and reads the charge out as either a “1” or a “0” depending upon the level of charge in the capacitor. In a write operation, the sense amplifier is over-powered and the memory cell capacitor is charged to an appropriate level.
Referring to FIG. 1, a DRAM memory cell 200 is illustrated. The cell 200 is illustrated as having a capacitor 202 and an access transistor 204. The capacitor 202 is used to store a charge. The charge represents a bit of information. The access transistor 204 acts as a switch for the capacitor 202. That is, the access transistor 204 controls when a charge is placed on the capacitor 202, and when a charge is discharged from the capacitor 202. A word line is coupled to a control gate of the access transistor 204. When a cell is read, the word line activates the control gate of the transistor 204. Once this happens, any charge (or lack of charge) stored on the capacitor 202 is shared with a conductive digit line coupled to the drain of the access transistor 204. This charge is then detected in the digit line by a sense amplifier and then processed to determine the bit state of the cell 200. Tiling a selected quantity of cells together, such that the cells along a given digit line do not share a common word line and the cells along a common word line do not share a common digit line, forms a memory array. A typical memory array contains thousands or millions of cells.
A plan view of a portion of a DRAM memory array is illustrated in FIG. 2. In this example of a DRAM memory array layout, cells are paired to share a common contact to the digit line (DL), which reduces the array size by eliminating duplication. This layout is arranged in an open digit line architecture wherein each memory cell 100 has an area equal to 6F2. That is, the area of a memory cell 100 in this layout is described as 6F2. As illustrated in FIG. 2, a box is drawn around a memory cell 100 to show the cell's outer boundary. Along the horizontal axis of the memory cell 100, the box includes one-half digit line contact feature 102, one word line feature 104, one capacitor feature 106, and one-half field oxide feature 108 for a total of three features. Along the vertical axis of the memory cell 100, the box contains two one-half field oxide features 112, 114 and one active area feature 116 for a total of two features. Therefore, the total area of a cell 100 is 3F*2F=6F2. Moreover, as FIG. 2 illustrates, pairs of cells in a row are isolated from other pairs of cells in the row. This is accomplished, in this example of an open digit line architecture, by grounding selective word lines (not shown). A discussion of DRAM circuit design including open digit line architecture is provided in Brent Keeth and Jacob Baker, DRAM Circuit Design, A Tutorial, 1-103 (IEEE Press 2001), which is incorporated herein by reference.
Referring to FIG. 2A, a schematic diagram of a portion of an open digit line DRAM array is illustrated, wherein the cells have an area of 6F2. As illustrated, sense amplifiers are coupled between digit line D1 and complementary digit line D1* and between D0 and complementary digit line D0*. Cells with a 1 bit can be expressed as having a +Vcc/2 stored on them and cells with a 0 bit can be expressed as having a −Vcc/2 stored on them. To read a memory cell, a digit line coupled to the cell and its complementary digit line are first initially equilibrated to Vcc/2 volts. Applying Vcc/2 bias voltage to the digit lines and then allowing the digit lines to float causes the digit lines to be equilibrated to Vcc/2 volts. Once the digit lines have been equilibrated to Vcc/2 volts, they remain in that state due to their capacitance. A voltage that is at least one transistor Vth above Vcc (this voltage is referred to as Vccp) is then applied to a word line coupled to the cell to be read. For example, if cell M1 is to be read, a voltage of Vccp is applied to word line WL0 after the digit lines D0 and D0* are equilibrated to Vcc/2. The charge on the capacitor of M1 is shared with digit line D0. In response to the shared charge, the voltage in digit line M1 either increases if cell M1 stored a 1 bit, or decreases if cell M1 stored a 0 bit. Thereafter, sense amplifier 220 compares the voltage in digit line D0 against the voltage in digit line D0*.
After the cell has been accessed, sensing occurs. Sensing is necessary to properly read the data and refresh the cells. A simplified illustration of a typical sense amplifier is shown in FIG. 3. As FIG. 3 illustrates, the sense amplifier includes a Psense-amp and a Nsense-amp. The Psense-amp includes a pMOS pair of transistors, and the Nsense-amp includes an nMOS pair of transistors. Also labeled in FIG. 3 is node ACT (for ACTive pull up) on the Psense-amp, and node NLAT* (Nsense-amp LATch) on the Nsense-amp. ACT and NLAT provide power and ground. Initially, NLAT* is biased to Vcc/2 and Act is biased to Vss or signal ground. Since, the digit line pair D0 and D0* are both at Vcc/2, the nMOS pair of transistors and the pMOS pair of transistors are turned off. When a cell is accessed that is coupled to either D0 or D0*, a voltage difference occurs between D0 and D0*. While one of the digit lines contains charge from the cell access, the other digit line serves as a reference for the sensing operation.
After the cell is accessed the sense amplifiers are generally fired sequentially, the Nsense-amp first, followed by the Psense-amp. The Nsense-amp is fired by pulling NLAT* toward ground. As the voltage difference between NLAT* and the digit lines approaches Vth, the nMOS transistor whose gate is connected to the higher voltage digit line begins to conduct. This conduction causes the low-voltage digit line to be discharged toward the NLAT* voltage. Ultimately, NLAT* will reach ground, and the digit line will be brought to ground potential. Sometime after the Nsense-amp fires, the Psense-amp is activated by bring the ACT toward Vcc. The Psense-amp operates in a complementary fashion to the Nsense-amp. With the low-voltage digit line approaching ground, there is a strong signal to drive the appropriate pMOS transistor into conduction. This conduction charges the high-voltage digit line toward ACT, ultimately reaching Vcc. The capacitor of the cell being read is refreshed during the sensing operation. This is accomplished by keeping the access transistor of the cell on when the Psense-amp is activated. The charge the capacitor of the cell had prior to accessing the cell is fully restored. That is, the charge will be restored to Vcc for a 1 bit and GND for a 0 bit.
What is needed is a ROM embedded DRAM utilizing a 6F2 architecture.